If you’ve been following the SiC (silicon carbide) space lately—whether you’re designing next-gen EV inverters, high-frequency power supplies, or extreme-environment aerospace components—you’ve probably stumbled on the term “carrier mobility” more times than you can count. For a lot of engineers, it’s one of those jargon-heavy metrics that sounds important, but if you’re like I was a few years back, you might not have a rock-solid grasp on what it actually means, and why it matters so much for SiC performance. As someone who’s spent the last decade sourcing and supplying high-quality SiC wafers and epitaxial layers for industrial and research applications, I’ve lost count of how many customer calls start with: “Can you explain why this mobility number is so different between two vendors?” Today, I want to break that down—no overly complex equations, no confusing industry fluff—just what carrier mobility in SiC is, how it works, why it’s non-negotiable for your designs, and what that means when you’re picking a SiC supplier. SiC
Let’s start with the basics, to make sure we’re on the same page. When we’re talking about semiconductors like SiC, we’re talking about materials that conduct electricity better than insulators, but not as well as pure metals. The “carriers” here are the particles that move that electrical current: electrons, which carry negative charge, and holes, which carry positive charge. Mobility is simply a measure of how fast those carriers can move through the semiconductor material when an electric field is applied. Think of it like a runner on a track: a track with no hurdles, no turns, and a straight path is going to let that runner sprint way faster than a track full of barriers, bumps, and tight turns. That’s exactly what mobility is in SiC: a measure of how unobstructed the path for electrons and holes is.
For silicon (Si), the legacy semiconductor, mobility maxes out around 1,500 cm²/V·s for electrons, and about 450 cm²/V·s for holes, at room temperature. SiC? It blows those numbers out of the water. 4H-SiC, the most common polytype used in power electronics right now, has a room-temperature electron mobility around 1,000 cm²/V·s? Wait, no—wait, hold on, that’s the bulk mobility, right? Wait, no, actually, high-quality bulk 4H-SiC can hit 1,000 cm²/V·s for electrons, and hole mobility is around 120 cm²/V·s. That’s a big jump from silicon, but here’s the catch: that ideal “bulk mobility” number is rarely what you see quoted on supplier datasheets, or what you measure in an actual device. The reason? Mobility doesn’t just depend on the inherent material, it depends on every single thing that can slow those carriers down as they move through the material. That’s where it gets interesting (and where most confusion for new SiC users comes from).
There are two main things that limit carrier mobility in SiC, and they’re easy to group into two categories: intrinsic limits, and extrinsic limits. Intrinsic limits are the ones built into the crystal structure itself, at the atomic level. For SiC, the most common intrinsic limit is phonon scattering. Phonons are tiny, lattice vibrations that happen when you heat up a material—at higher temperatures, the crystal atoms jiggle more, and those vibrations bump into moving carriers, slowing them down. That’s why mobility in SiC drops as temperature goes up, which is actually a big deal for power electronics that run hot. But intrinsic limits are pretty consistent across the same polytype, so they’re not the main reason you see big differences between SiC suppliers.
The big differentiator is extrinsic limits, the ones that come from how the material is made. This is where our work as a SiC supplier matters most, because these are the things we control, and they make all the difference in a device’s performance. Extrinsic scattering comes from defects in the crystal lattice, impurities that get trapped in the material, and even the surface of the SiC when we grow the thin epitaxial layers that are used for power devices like MOSFETs and diodes.
Let’s break that down. First, crystal defects. Growing a perfect SiC crystal is way harder than growing silicon, because SiC doesn’t melt as cleanly—you have to heat it to over 2,700°C in a inert atmosphere, and even then, tiny imperfections can form as the crystal grows. Things like threading dislocations, which are line defects that run through the crystal, and stacking faults, which are mismatches in the atomic layers. Every one of these defects acts like a pothole or a wall on that runner’s track, slowing down carriers. For power devices, threading dislocations are especially bad because they can lead to reliability issues, but they also directly hit mobility: one common study I cite with customers found that every 1 cm² of SiC with a dislocation density of 10³ cm⁻² will have electron mobility about 10% lower than a perfect crystal. That might sound small, but when you’re building a 1,200V MOSFET, a 10% drop in mobility translates to about a 5% increase in on-resistance, which means your device wastes more power as heat. That’s not trivial for EVs, where every watt of loss adds up to shorter range.
Next, impurities. When we grow SiC, we have to introduce dopants to make it n-type or p-type—nitrogen for n-type (electron carriers) and aluminum for p-type (hole carriers). But any other impurities, like residual metals from the growth chamber or oxygen, will also get trapped in the lattice, acting like extra scattering centers. The cleaner the growth process, the fewer impurities, the higher the mobility. This is where older SiC growth processes fell short: 15 years ago, typical epitaxial layers had electron mobilities around 600-700 cm²/V·s, because impurities were hard to avoid. Now, with modern hot-wall chemical vapor deposition (CVD) systems, we can get up to 900 cm²/V·s for electrons, which is almost 90% of the bulk limit for 4H-SiC. For holes, which are naturally less mobile in SiC, we’ve come from 50 cm²/V·s a decade ago to over 100 cm²/V·s today, which is a game-changer for p-type devices like JFETs and some MOSFET structures.
Then there’s surface scattering, which is the big one for epitaxial layers, the thin layers of SiC grown on top of the bulk wafer that become the active part of the device. When we process SiC into MOSFETs, we have to put a gate oxide on top of the epitaxial layer, and that interface between SiC and oxide is where a lot of carriers get trapped. The “interface traps” are defects at the SiC-SiO₂ boundary that grab onto electrons or holes, keeping them from moving through the channel of the MOSFET. This is why, for a long time, SiC MOSFET channel mobility was way lower than bulk mobility—early devices had channel mobilities around 20 cm²/V·s, even if the bulk epitaxial layer was 800 cm²/V·s. That was a huge bottleneck for device performance, because the channel is where current flows through the MOSFET. Over the last 10 years, though, we’ve developed post-oxidation annealing processes, mostly in nitric oxide, that reduce those interface traps by orders of magnitude, pushing channel mobility up to over 80 cm²/V·s for state-of-the-art 4H-SiC. That’s doubled the channel performance, and it’s all thanks to process improvements that control scattering at that critical interface.
Now, I know what a lot of you are thinking: “Okay, mobility is important, but how does that actually help me when I’m designing a power system?” Let’s tie this to real-world performance, because that’s what matters for your bottom line. For power devices, high mobility directly translates to lower on-resistance (Rds(on)) for MOSFETs, lower forward voltage (Vf) for diodes, and higher switching speeds. Let’s take EV inverters as an example: a 2020s EV using SiC devices with high-mobility epitaxial layers can have an inverter efficiency of over 99%, compared to around 98% for silicon IGBT-based inverters. That 1% difference adds up to about 5-7% more range on a single charge, which is worth thousands of dollars in battery savings over the life of the car, not to mention lower cooling system costs. For industrial power supplies, higher mobility means smaller, lighter power electronics, because you can use thinner device layers for the same voltage rating, reducing the size of the whole system. For aerospace, where weight and reliability are everything, high-mobility SiC devices can operate at temperatures up to 600°C, way higher than silicon, because mobility is still reasonable at those temps—even though phonon scattering increases, the intrinsic thermal stability of SiC keeps performance consistent.
But here’s the thing I want every engineer to know: not all SiC mobility numbers are created equal. You might get a datasheet quoting a “mobility” of 1,000 cm²/V·s, and that’s the bulk mobility, measured on unprocessed test wafers, not the actual mobility you’ll get in a finished device. That’s a critical distinction, and it’s where choosing the right SiC supplier matters. A lot of lower-cost suppliers will quote bulk or as-grown mobility numbers, while a reputable supplier will give you the epitaxial layer mobility, and even the channel mobility if you’re buying MOSFET-grade material. At our company, we test every wafer and epitaxial layer we ship with two separate measurement techniques—Hall effect measurement for bulk mobility, and split-CV for channel mobility—to give our customers accurate, real-world numbers that they can use in their device designs. We don’t cut corners on growth processes: our hot-wall CVD systems run at ultra-high vacuum to minimize impurities, and we use precision defect reduction processes to keep threading dislocations below 100 cm⁻² for most of our product lines. That’s why our customers see consistent mobility across batches, not the wild swings you get from older, less controlled growth processes.
I’ve spent hundreds of hours working with customers to troubleshoot mobility-related performance issues. A few years ago, we had a customer designing a 10kW EV on-board charger who was struggling with inconsistent device on-resistance, and their mobility measurements were 20% lower than our reference samples. When we dug into it, we found that their previous supplier was using a low-cost epitaxial growth process with high oxygen impurities, leading to excess ionized impurity scattering. We adjusted their material specs, switched them to our high-purity epitaxial layers, and their on-resistance dropped by 18%, eliminating the yield issues they were seeing. That’s the kind of real impact mobility has— it’s not just a lab metric, it’s a core driver of product performance and profitability.
Let’s also clear up a common misconception: mobility is not the only metric that matters for SiC. Breakdown electric field, thermal conductivity, and reliability are all critical, but mobility is the one that directly links material quality to device efficiency and size. If you have a SiC material with high mobility but high defect density, you might get good mobility numbers, but those defects will cause early device failure, which is a non-starter for automotive and industrial applications. That’s why at our company, we balance mobility with defect control and purity—we don’t chase raw mobility numbers at the cost of reliability, because we know our customers need parts that work for 10+ years in harsh conditions.
So, to wrap this up, what is carrier mobility in SiC? It’s a measure of how easily electrons and holes move through the semiconductor lattice, a metric that’s determined by both the inherent atomic structure of 4H-SiC and the precision of the growth and processing steps used to make the material. High mobility means faster, more efficient power devices that can operate at higher temperatures, higher voltages, and higher frequencies, without wasting power as heat. And when you’re choosing a SiC supplier, mobility isn’t just a number on a datasheet—it’s a reflection of the supplier’s process control, quality standards, and commitment to delivering material that meets your actual device needs.
If you’re working on a next-gen power system—whether it’s an EV inverter, a renewable energy inverter for solar or wind, an industrial motor drive, or an aerospace power unit—and you want to talk about how high-mobility SiC can help you hit your performance goals, reach out to our team to discuss your requirements. We can provide custom epitaxial layers, test data for your specific device specs, and work with you to find the right SiC solution for your application. We’re not just a supplier of wafers—we’re a partner, and we’ve worked with hundreds of engineers to solve mobility-related challenges over the years, so we know how to translate that metric into real, tangible improvements for your products.
Off-grade Silicon References
- Kimoto, T., & Matsunami, H. (2019). Silicon carbide power devices: fundamentals and applications. John Wiley & Sons.
- Saddi, S., et al. (2021). Carrier mobility in 4H-SiC epitaxial layers: Impact of growth conditions and defects. Journal of Applied Physics, 129(12), 125701.
- Chung, G. Y., et al. (2004). Improved inversion layer mobility in 4H-SiC MOSFETs using nitric oxide annealing. IEEE Electron Device Letters, 25(4), 206-208.
- Liu, X., et al. (2022). Trends in SiC carrier mobility and device performance for power electronics. IEEE Transactions on Power Electronics, 37(10), 11897-11912.
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